Tick–tock model

Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick–tock is a model that refreshes one side of a binary system each release cycle.

History

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (sometimes introducing new instructions, as with Broadwell, released in late 2014) and every "tock" designated a new microarchitecture. These occurred roughly every year to 18 months. In 2014, Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture not considered a new generation in and of itself.

In March 2016, Intel announced in a Form 10-K report that it deprecated the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization. The first optimization of the Skylake architecture was Kaby Lake. Intel then announced a second optimization, Coffee Lake, making a total of four generations at 14 nm.

Roadmap

Pentium 4 / Core / Xeon roadmap

Atom roadmap

With Silvermont Intel tried to start Tick-Tock in Atom architecture but problems with the 10 nm process did not allow to do this. In the table below instead of Tick-Tock steps Process-Architecture-Optimization are used. There is no official confirmation that Intel uses Process-Architecture-Optimization for Atom but it allows us to understand what changes happened in each generation.

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL; the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology. In 2018, Intel announced that Knights Landing and all further Xeon Phi CPU models were discontinued. However, Intel's Sierra Forest and subsequent Atom-based Xeon CPUs are likely a spiritual successor to Xeon Phi.

Both

See also

• List of Intel CPU microarchitectures
• Transient execution CPU vulnerability

References

External links

• "Intel Tick–Tock Model of Architecture & Silicon Cadence". intel.com. Intel Corporation.
• Intel Tick–Tock Model at IDF 2009, Anandtech.com
• "Intel Tick–Tock Model at IDF 2011" (PDF). intel.com. Intel Corporation. p. 21.

1. Tick tock
2. Process–architecture–optimization model
3. List of Intel CPU microarchitectures
4. Ivy Bridge (microarchitecture)
5. Granite Rapids
6. Tick Tock (Clean Bandit and Mabel song)
7. Sierra Forest
8. Die shrink
9. Sapphire Rapids
10. Silvermont
11. Nehalem (microarchitecture)
12. Penryn (microarchitecture)
13. Intel
14. MacOS
15. Hazard (computer architecture)
16. Adder (electronics)
17. Tejas and Jayhawk
18. Memory-mapped I/O and port-mapped I/O
19. Emerald Rapids
20. Translation lookaside buffer