This generational list of Intel processors attempts to present all of Intel's processors from the 4-bit 4004 (1971) to the present high-end offerings. Concise technical data is given for each product.
An iterative refresh of Raptor Lake-S desktop processors, called the 14th generation of Intel Core, was launched on October 17, 2023.
CPUs in bold below feature ECC memory support only when paired with a motherboard based on the W680 chipset according to each respective Intel Ark product page.
Mobile - Raptor Lake-HX Refresh (codenamed "Raptor Lake") (14th Gen)
An iterative refresh of Raptor Lake-HX mobile processors, called the 14th generation of Intel Core, was launched on Jan 9, 2024
Desktop (codenamed "Raptor Lake") (13th Gen)
Mobile (codenamed "Raptor Lake") (13th Gen)
12th generation Core
Desktop (codenamed "Alder Lake")
Mobile (codenamed "Alder Lake")
11th generation Core
Desktop (codenamed "Rocket Lake")
Mobile (codenamed "Tiger Lake")
10th generation Core
Desktop (codenamed "Comet Lake")
Mobile (codenamed "Comet Lake", "Ice Lake", and "Amber Lake")
9th generation Core
Desktop (codenamed "Coffee Lake Refresh")
8th generation Core
Desktop (codenamed "Coffee Lake")
Mobile (codenamed "Coffee Lake", "Amber Lake" and "Whiskey Lake")
7th generation Core
Desktop (codenamed "Kaby Lake" and "Skylake-X")
Mobile (codenamed "Kaby Lake" and "Apollo Lake")
All processors
All processors are listed in chronological order.
The 4-bit processors
Intel 4004
First microprocessor (single-chip IC processor)
Introduced November 15, 1971
Clock rate 740 kHz
0.07 MIPS
Bus width: 4 bits (multiplexed address/data due to limited pins)
PMOS
2,300 transistors at 10 μm
Addressable memory 640 bytes
Program memory 4 KB (4096 B)
Originally designed to be used in Busicom calculator
MCS-4 family:
4004 – CPU
4001 – ROM & 4-bit Port
4002 – RAM & 4-bit Port
4003 – 10-bit Shift Register
4008 – Memory+I/O Interface
4009 – Memory+I/O Interface
4211 – General Purpose Byte I/O Port
4265 – Programmable General Purpose I/O Device
4269 – Programmable Keyboard Display Device
4289 – Standard Memory Interface for MCS-4/40
4308 – 8192-bit (1024 × 8) ROM w/ 4-bit I/O Ports
4316 – 16384-bit (2048 × 8) Static ROM
4702 – 2048-bit (256 × 8) EPROM
4801 – 5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A
Intel 4040
Introduced in 1974 by Intel
Clock speed was 740 kHz (same as the 4004 microprocessor)
3,000 transistors
Interrupt features were available
Programmable memory size: 8 KB (8192 B)
640 bytes of data memory
24-pin DIP
The 8-bit processors
8008
Introduced April 1, 1972
Clock rate 500 kHz (8008-1: 800 kHz)
0.05 MIPS
Bus width: 8 bits (multiplexed address/data due to limited pins)
Enhancement load PMOS logic
3,500 transistors at 10 μm
Addressable memory 16 KB
Typical in early 8-bit microcomputers, dumb terminals, general calculators, bottling machines
Developed in tandem with 4004
Originally intended for use in the Datapoint 2200 microcomputer
Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships
8080
Introduced April 1, 1974
Clock rate 2 MHz (very rare 8080B: 3 MHz)
0.29 MIPS
Data bus width: 8 bits, address bus: 16 bits
Enhancement load NMOS logic
4,500 transistors at 6 μm
Assembly language downward compatible with 8008
Addressable memory 64 KB (64 × 1024 B)
Up to 10× the performance of the 8008
Used in e.g. the Altair 8800, traffic light controller, cruise missile
Required six support chips versus 20 for the 8008
8085
Introduced March 1976
Clock rate 3 MHz
0.37 MIPS
Data bus width: 8 bits, address bus: 16 bits
Depletion load NMOS logic
6,500 transistors at 3 μm
Binary compatible downward with the 8080
Used in Toledo scales. Also used as a computer peripheral controller – modems, hard disks, printers, etc.
CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable
Microcontrollers
They are ICs with CPU, RAM, ROM (or PROM or EPROM), I/O Ports, Timers & Interrupts
Intel 8243 – Input/Output Expander. The available 28-pin PLCC version in sampling for first quarter of 1986.
Intel 8244 – General Purpose Graphics Display Device (ASIC NTSC/SECAM)
Intel 8245 – General Purpose Graphics Display Device (ASIC PAL)
Intel 8051
Single accumulator Harvard architecture
MCS-51 family:
8031 – 8-bit Control-Oriented Microcontroller
8032 – 8-bit Control-Oriented Microcontroller
8044 – High Performance 8-bit Microcontroller
8344 – High Performance 8-bit Microcontroller
8744 – High Performance 8-bit Microcontroller
8051 – 8-bit Control-Oriented Microcontroller
8052 – 8-bit Control-Oriented Microcontroller
8054 – 8-bit Control-Oriented Microcontroller
8058 – 8-bit Control-Oriented Microcontroller
8351 – 8-bit Control-Oriented Microcontroller
8352 – 8-bit Control-Oriented Microcontroller
8354 – 8-bit Control-Oriented Microcontroller
8358 – 8-bit Control-Oriented Microcontroller
8751 – 8-bit Control-Oriented Microcontroller
8752 – 8-bit Control-Oriented Microcontroller
8754 – 8-bit Control-Oriented Microcontroller
8758 – 8-bit Control-Oriented Microcontroller
Intel 80151
Single accumulator Harvard architecture
MCS-151 family:
80151 – High Performance 8-bit Control-Oriented Microcontroller
83151 – High Performance 8-bit Control-Oriented Microcontroller
87151 – High Performance 8-bit Control-Oriented Microcontroller
80152 – High Performance 8-bit Control-Oriented Microcontroller
83152 – High Performance 8-bit Control-Oriented Microcontroller
Intel 80251
Single accumulator Harvard architecture
MCS-251 family:
80251 – 8/16/32-bit Microcontroller
80252 – 8/16/32-bit Microcontroller
80452 – 8/16/32-bit Microcontroller
83251 – 8/16/32-bit Microcontroller
87251 – 8/16/32-bit Microcontroller
87253 – 8/16/32-bit Microcontroller
MCS-96 family
8061 – 16-bit Microcontroller (parent of MCS-96 family ROMless With A/D, most sold to Ford)
8094 – 16-bit Microcontroller (48-Pin ROMLess Without A/D)
8095 – 16-bit Microcontroller (48-Pin ROMLess With A/D)
8096 – 16-bit Microcontroller (68-Pin ROMLess Without A/D)
8097 – 16-bit Microcontroller (68-Pin ROMLess With A/D)
8394 – 16-bit Microcontroller (48-Pin With ROM Without A/D)
8395 – 16-bit Microcontroller (48-Pin With ROM With A/D)
8396 – 16-bit Microcontroller (68-Pin With ROM Without A/D)
8397 – 16-bit Microcontroller (68-Pin With ROM With A/D)
8794 – 16-bit Microcontroller (48-Pin With EROM Without A/D)
8795 – 16-bit Microcontroller (48-Pin With EROM With A/D)
8796 – 16-bit Microcontroller (68-Pin With EROM Without A/D)
8797 – 16-bit Microcontroller (68-Pin With EROM With A/D)
8098 – 16-bit Microcontroller
8398 – 16-bit Microcontroller
8798 – 16-bit Microcontroller
80196 – 16-bit Microcontroller
83196 – 16-bit Microcontroller
87196 – 16-bit Microcontroller
80296 – 16-bit Microcontroller
The bit-slice processor
3000 family
Introduced in the third quarter of 1974, these bit-slicing components used bipolar Schottky transistors. Each component implemented two bits of a processor function; packages could be interconnected to build a processor with any desired word length.
Members of the 3000 family:
3001 – Microcontrol Unit
3002 – 2-bit Arithmetic Logic Unit slice
3003 – Look-ahead Carry Generator
3205 – High-performance 1 of 8 Binary Decoder
3207 – Quad Bipolar-to-MOS Level Shifter and Driver
3208 – Hex Sense Amp and Latch for MOS Memories
3210 – TTL-to-MOS Level Shifter and High Voltage Clock Driver
3211 – ECL-to-MOS Level Shifter and High Voltage Clock Driver
3212 – Multimode Latch Buffer
3214 – Interrupt Control Unit
3216 – Parallel, Inverting Bi-Directional Bus Driver
3222 – Refresh Controller for 4K (4096 B) NMOS DRAMs
3226 – Parallel, Inverting Bi-Directional Bus Driver
3232 – Address Multiplexer and Refresh Counter for 4K DRAMs
3242 – Address Multiplexer and Refresh Counter for 16K (16 × 1024 B) DRAMs
3245 – Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
3246 – Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
3404 – High-performance 6-bit Latch
3408 – Hex Sense Amp and Latch for MOS Memories
3505 – Next generation processor
Bus width 2n bits data/address (depending on number n of slices used)
The 16-bit processors: MCS-86 family
8086
Introduced June 8, 1978
Clock rates:
5 MHz, 0.33 MIPS
8 MHz, 0.66 MIPS
10 MHz, 0.75 MIPS
The memory is divided into odd and even banks. It accesses both banks concurrently to read 16 bits of data in one clock cycle
Data bus width: 16 bits, address bus: 20 bits
29,000 transistors at 3 μm
Addressable memory 1 megabyte (10242B)
Up to 10× the performance of 8080
First used in the Compaq Deskpro IBM PC-compatible computers. Later used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line)
Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.
The first x86 CPU
Later renamed the iAPX 86
8088
Introduced June 1, 1979
Clock rates:
4.77 MHz, 0.33 MIPS
8 MHz, 0.66 MIPS
16-bit internal architecture
External data bus width: 8 bits, address bus: 20 bits
29,000 transistors at 3 μm
Addressable memory 1 megabyte
Identical to 8086 except for its 8-bit external bus (hence an 8 instead of a 6 at the end); identical Execution Unit (EU), different Bus Interface Unit (BIU)
Used in IBM PC and PC-XT and compatibles
Later renamed the iAPX 88
80186
Introduced 1982
Clock rates
6 MHz, > 1 MIPS
55,000 transistors
Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (these were at fixed addresses which differed from the IBM PC, although it was used by several PC compatible vendors such as Australian company Cleveland)
Added a few opcodes and exceptions to the 8086 design, otherwise identical instruction set to 8086 and 8088
BOUND, ENTER, LEAVE
INS, OUTS
IMUL imm, PUSH imm, PUSHA, POPA
RCL/RCR/ROL/ROR/SHL/SHR/SAL/SAR reg, imm
Address calculation and shift operations are faster than 8086
Used mostly in embedded applications – controllers, point-of-sale systems, terminals, and the like
Used in several non-PC compatible DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server
Later renamed to iAPX 186
80188
A version of the 80186 with an 8-bit external data bus
Later renamed the iAPX 188
80286
Introduced February 1, 1982
Clock rates:
6 MHz, 0.9 MIPS
8 MHz, 10 MHz, 1.5 MIPS
12.5 MHz, 2.66 MIPS
16 MHz, 20 MHz and 25 MHz available.
Data bus width: 16 bits, address bus: 24 bits
Included memory protection hardware to support multitasking operating systems with per-process address space.
134,000 transistors at 1.5 μm
Addressable memory 16 MB
Added protected-mode features to 8086 with essentially the same instruction set
3–6× the performance of the 8086
Widely used in IBM PC AT and AT clones contemporary to it
32-bit processors: the non-x86 microprocessors
iAPX 432
Introduced January 1, 1981 as Intel's first 32-bit microprocessor
Multi-chip CPU
Object/capability architecture
Microcoded operating system primitives
One terabyte virtual address space
Hardware support for fault tolerance
Two-chip General Data Processor (GDP), consists of 43201 and 43202
43203 Interface Processor (IP) interfaces to I/O subsystem
43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
43205 Memory Control Unit (MCU)
Architecture and execution unit internal data base paths: 32 bits
Clock rates:
5 MHz
7 MHz
8 MHz
i960 a.k.a. 80960
Introduced April 5, 1988
RISC-like 32-bit architecture
Predominantly used in embedded systems
Evolved from the capability processor developed for the BiiN joint venture with Siemens
Many variants identified by two-letter suffixes
i860 a.k.a. 80860
Introduced February 26, 1989
RISC 32/64-bit architecture, with floating point pipeline characteristics very visible to programmer
Used in the Intel iPSC/860 Hypercube parallel supercomputer
Mid-life kicker in the i870 processor (primarily a speed bump, some refinement/extension of instruction set)
Used in the Intel Delta massively parallel supercomputer prototype, emplaced at California Institute of Technology
Used in the Intel Paragon massively parallel supercomputer, emplaced at Sandia National Laboratory
XScale
Introduced August 23, 2000
32-bit RISC microprocessor based on the ARM architecture
Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors
32-bit processors: the 80386 range
80386DX
Introduced October 17, 1985
Clock rates:
16 MHz, 5 MIPS
20 MHz, 6 to 7 MIPS, introduced February 16, 1987
25 MHz, 7.5 MIPS, introduced April 4, 1988
33 MHz, 9.9 MIPS (9.4 SPECint92 on Compaq/i 16 KB L2), introduced April 10, 1989
Data bus width: 32 bits, address bus: 32 bits
275,000 transistors at 1 μm
Addressable memory 4 GB (4 × 10243 B)
Virtual memory 64 TB (64 × 10244 B)
First x86 chip to handle 32-bit data sets
Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Windows, and macOS
First used by Compaq in the Deskpro 386. Used in desktop computing
Unlike the DX naming convention of the 486 chips, it had no math co-processor
Later renamed Intel386 DX
80386SX
Introduced June 16, 1988
Clock rates:
16 MHz, 2.5 MIPS
20 MHz, 3.1 MIPS, introduced January 25, 1989
25 MHz, 3.9 MIPS, introduced January 25, 1989
33 MHz, 5.1 MIPS, introduced October 26, 1992
32-bit internal architecture
External data bus width: 16 bits
External address bus width: 24 bits
275,000 transistors at 1 μm
Addressable memory 16 MB
Virtual memory 64 TB
Narrower buses enable low-cost 32-bit processing
Used in entry-level desktop and portable computing
No math co-processor
No commercial software used protected mode or virtual storage for many years
Later renamed Intel386 SX
80376
Introduced January 16, 1989; discontinued June 15, 2001
Variant of 386SX intended for embedded systems
No "real mode", starts up directly in "protected mode"
Replaced by much more successful 80386EX from 1994
80386SL
Introduced October 15, 1990
Clock rates:
20 MHz, 4.21 MIPS
25 MHz, 5.3 MIPS, introduced September 30, 1991
32-bit internal architecture
External bus width: 16 bits
855,000 transistors at 1 μm
Addressable memory 4 GB
Virtual memory 64 TB
First chip specifically made for portable computers because of low power consumption of chip
Highly integrated, includes cache, bus, and memory controllers
80386EX
Introduced August 1994
Variant of 80386SX intended for embedded systems
Static core (i.e. may run as slowly (and thus, power efficiently) as desired) down to full halt
On-chip peripherals:
Clock and power management
Timers/counters
Watchdog timer
Serial I/O units (sync and async) and parallel I/O
DMA
RAM refresh
JTAG test logic
Significantly more successful than the 80376
Used aboard several orbiting satellites and microsatellites
Used in NASA's FlightLinux project
32-bit processors: the 80486 range
80486DX
Introduced April 10, 1989
Clock rates:
25 MHz, 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
33 MHz, 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
50 MHz, 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991
Bus width: 32 bits
1.2 million transistors at 1 μm; the 50 MHz was at 0.8 μm
Addressable memory 4 GB
Virtual memory 64 TB
Level 1 cache of 8 KB on chip
Math coprocessor on chip
50× performance of the 8088
Officially named Intel486 DX
Used in desktop computing and servers
Family 4 model 1
80486SX
Introduced April 22, 1991
Clock rates:
16 MHz, 13 MIPS
20 MHz, 16.5 MIPS, introduced September 16, 1991
25 MHz, 20 MIPS (12 SPECint92), introduced September 16, 1991
33 MHz, 27 MIPS (15.86 SPECint92), introduced September 21, 1992
Bus width: 32 bits
1.185 million transistors at 1 μm and 900,000 at 0.8 μm
Addressable memory 4 GB
Virtual memory 64 TB
Identical in design to 486DX but without a math coprocessor. The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, they must add 487SX which was actually a 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 effectively turned on
Officially named Intel486 SX
Used in low-cost entry to 486 CPU desktop computing, as well as extensively in low cost mobile computing
Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
77 million transistors
Micro-FCPGA, Micro-FCBGA processor package
Heart of the Intel mobile Centrino system
400 MHz NetBurst-style system bus
Family 6 model 9
Variants
900 MHz (ultra-low voltage)
1.0 GHz (ultra-low voltage)
1.1 GHz (low voltage)
1.2 GHz (low voltage)
1.3 GHz
1.4 GHz
1.5 GHz
1.6 GHz
1.7 GHz
Dothan 0.09 μm (90 nm) process technology
Introduced May 2004
2 MB L2 cache
140 million transistors
Revised data prefetch unit
400 MHz NetBurst-style system bus
21 W TDP
Family 6 model 13
Variants
1.00 GHz (Pentium M 723) (ultra-low voltage, 5 W TDP)
1.10 GHz (Pentium M 733) (ultra-low voltage, 5 W TDP)
1.20 GHz (Pentium M 753) (ultra-low voltage, 5 W TDP)
1.30 GHz (Pentium M 718) (low voltage, 10 W TDP)
1.40 GHz (Pentium M 738) (low voltage, 10 W TDP)
1.50 GHz (Pentium M 758) (low voltage, 10 W TDP)
1.60 GHz (Pentium M 778) (low voltage, 10 W TDP)
1.40 GHz (Pentium M 710)
1.50 GHz (Pentium M 715)
1.60 GHz (Pentium M 725)
1.70 GHz (Pentium M 735)
1.80 GHz (Pentium M 745)
2.00 GHz (Pentium M 755)
2.10 GHz (Pentium M 765)
Dothan 533 0.09 μm (90 nm) process technology
Introduced Q1 2005
Same as Dothan except with a 533 MHz NetBurst-style system bus and 27 W TDP
Variants
1.60 GHz (Pentium M 730)
1.73 GHz (Pentium M 740)
1.86 GHz (Pentium M 750)
2.00 GHz (Pentium M 760)
2.13 GHz (Pentium M 770)
2.26 GHz (Pentium M 780)
Stealey 0.09 μm (90 nm) process technology
Introduced Q2 2007
512 KB L2, 3 W TDP
Variants
600 MHz (A100)
800 MHz (A110)
Celeron M
Banias-512 0.13 μm process technology
Introduced March 2003
64 KB L1 cache
512 KB L2 cache (integrated)
SSE2 SIMD instructions
No SpeedStep technology, is not part of the 'Centrino' package
Family 6 model 9
Variants
310, 1.20 GHz
320, 1.30 GHz
330, 1.40 GHz
340, 1.50 GHz
Dothan-1024 90 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE2 SIMD instructions
No SpeedStep technology, is not part of the 'Centrino' package
Variants
350, 1.30 GHz
350J, 1.30 GHz, with Execute Disable bit
360, 1.40 GHz
360J, 1.40 GHz, with Execute Disable bit
370, 1.50 GHz, with Execute Disable bit
Family 6, Model 13, Stepping 8
380, 1.60 GHz, with Execute Disable bit
390, 1.70 GHz, with Execute Disable bit
Yonah-1024 65 nm process technology
64 KB L1 cache
1 MB L2 cache (integrated)
SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
No SpeedStep technology, is not part of the 'Centrino' package
Variants
410, 1.46 GHz
420, 1.60 GHz,
423, 1.06 GHz (ultra-low voltage)
430, 1.73 GHz
440, 1.86 GHz
443, 1.20 GHz (ultra-low voltage)
450, 2.00 GHz
Intel Core
Yonah 0.065 μm (65 nm) process technology
Introduced January 2006
533/667 MHz front-side bus
2 MB (Shared on Duo) L2 cache
SSE3 SIMD instructions
31W TDP (T versions)
Family 6, Model 14
Variants:
Intel Core Duo T2700 2.33 GHz
Intel Core Duo T2600 2.16 GHz
Intel Core Duo T2500 2 GHz
Intel Core Duo T2450 2 GHz
Intel Core Duo T2400 1.83 GHz
Intel Core Duo T2300 1.66 GHz
Intel Core Duo T2050 1.6 GHz
Intel Core Duo T2300e 1.66 GHz
Intel Core Duo T2080 1.73 GHz
Intel Core Duo L2500 1.83 GHz (low voltage, 15 W TDP)
Intel Core Duo L2400 1.66 GHz (low voltage, 15 W TDP)
Intel Core Duo L2300 1.5 GHz (low voltage, 15 W TDP)
Intel Core Duo U2500 1.2 GHz (ultra-low voltage, 9 W TDP)
Intel Core Solo T1350 1.86 GHz (533 FSB)
Intel Core Solo T1300 1.66 GHz
Intel Core Solo T1200 1.5 GHz
Dual-Core Xeon LV
Sossaman 0.065 μm (65 nm) process technology
Introduced March 2006
Based on Yonah core, with SSE3 SIMD instructions
667 MHz frontside bus
2 MB shared L2 cache
Variants
2.0 GHz
32-bit processors: NetBurst microarchitecture
Pentium 4
0.18 μm process technology (1.40 and 1.50 GHz)
Introduced November 20, 2000
L2 cache was 256 KB Advanced Transfer cache (integrated)
Processor package Style was PGA423, PGA478
System bus clock rate 400 MHz
SSE2 SIMD Extensions
42 million transistors
Used in desktops and entry-level workstations
0.18 μm process technology (1.7 GHz)
Introduced April 23, 2001
See the 1.4 and 1.5 chips for details
0.18 μm process technology (1.6 and 1.8 GHz)
Introduced July 2, 2001
See 1.4 and 1.5 chips for details
Core voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in battery optimized mode
Power <1 watt in battery optimized mode
Used in full-size and then light mobile PCs
0.18 μm process technology Willamette (1.9 and 2.0 GHz)
Introduced August 27, 2001
See 1.4 and 1.5 chips for details
Family 15 model 1
Pentium 4 (2 GHz, 2.20 GHz)
Introduced January 7, 2002
Pentium 4 (2.4 GHz)
Introduced April 2, 2002
0.13 μm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8 (OEM), 3.0 (OEM) GHz)
Improved branch prediction and other microcodes tweaks
512 KB integrated L2 cache
55 million transistors
400 MHz system bus
Family 15 model 2
0.13 μm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
533 MHz system bus. (3.06 includes Intel's Hyper-Threading technology)
0.13 μm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
800 MHz system bus (all versions include Hyper-Threading)
6500 to 10,000 MIPS
Itanium(chronological entry – new non-x86 architecture)
Introduced 2001
Xeon (32-bit NetBurst)
Official designation now Xeon; i.e. not "Pentium 4 Xeon"
Xeon 1.4, 1.5, 1.7 GHz
Introduced May 21, 2001
L2 cache was 256 KB Advanced Transfer cache (integrated)
Processor package Organic Land Grid Array 603 (OLGA 603)
System bus clock rate 400 MHz
SSE2 SIMD Extensions
Used in high-performance and mid-range dual processor enabled workstations
Xeon 2.0 GHz and up to 3.6 GHz
Introduced September 25, 2001
Itanium 2(chronological entry – new non-x86 architecture)
Introduced July 2002
See main entry
Mobile Pentium 4-M
0.13 μm process technology
55 million transistors
512 KB L2 cache
BUS a 400 MHz
Supports up to 1 GB of DDR 266 MHz memory
Supports ACPI 2.0 and APM 1.2 System Power Management
1.3–1.2 V (SpeedStep)
Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
Sleep power 5 W (1.2 V)
Deeper sleep power 2.9 W (1.0 V)
1.40 GHz – 23 April 2002
1.50 GHz – 23 April 2002
1.60 GHz – 4 March 2002
1.70 GHz – 4 March 2002
1.80 GHz – 23 April 2002
1.90 GHz – 24 June 2002
2.00 GHz – 24 June 2002
2.20 GHz – 16 September 2002
2.40 GHz – 14 January 2003
2.50 GHz – 16 April 2003
2.60 GHz – 11 June 2003
Pentium 4 EE
Introduced September 2003
"Extreme Edition"
Built from the Xeon's "Gallatin" core, but with 2 MB cache
Pentium 4E
Introduced February 2004
Built on 0.09 μm (90 nm) process technology Prescott (2.4 A, 2.8, 2.8 A, 3.0, 3.2, 3.4, 3.6, 3.8 ) 1 MB L2 cache
533 MHz system bus (2.4A and 2.8A only)
800 MHz system bus (all other models)
125 million transistors in 1 MB models
169 million transistors in 2 MB models
Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth
7500 to 11,000 MIPS
LGA 775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
The 6xx series has 2 MB L2 cache and Intel 64
64-bit processors: IA-64
New instruction set, not at all related to x86
Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly (see its 2001 market reception and 2006 architectural changes)
Itanium
Code name Merced
Family 7
Released May 29, 2001
733 MHz and 800 MHz
2 MB cache
All recalled and replaced by Itanium 2
Itanium 2
Family 0x1F
Released July 2002
900 MHz – 1.6 GHz
McKinley 900 MHz 1.5 MB cache, Model 0x0
McKinley 1 GHz, 3 MB cache, Model 0x0
Deerfield 1 GHz, 1.5 MB cache, Model 0x1
Madison 1.3 GHz, 3 MB cache, Model 0x1
Madison 1.4 GHz, 4 MB cache, Model 0x1
Madison 1.5 GHz, 6 MB cache, Model 0x1
Madison 1.67 GHz, 9 MB cache, Model 0x1
Hondo 1.4 GHz, 4 MB cache, dual-core MCM, Model 0x1
4 physical cores/4 threads (except for i5-2390T which has 2 physical cores/4 threads)
32+32 KB (per core) L1 cache
256 KB (per core) L2 cache
6 MB L3 cache (except for i5-2390T which has 3 MB)
995 million transistors
Introduced January, 2011
Socket 1155 LGA
2-channel DDR3-1333
Variants ending in 'S' have a peak TDP of 65 W; others, 95 W except where noted
Variants ending in 'K' have unlocked multipliers; others cannot be overclocked
Integrated GPU
i5-2500T has a peak GPU turbo frequency of 1.25 GHz, others 1.1 GHz
Variants ending in 'T' have GPUs running at a base frequency of 650 MHz; others at 850 MHz
Variants ending in '5' or 'K' have Intel HD Graphics 3000 (12 execution units), except i5-2550K which has no GPU; others have Intel HD Graphics 2000 (6 execution units)
Variants ending in 'P' and the i5-2550K have no GPU
Variants
i5-2390T, 2.7 GHz/3.5 GHz Turbo Boost (35 W max. TDP)
i5-2500T, 2.3 GHz/3.3 GHz Turbo Boost (45 W max. TDP)
Note: this list does not say that all processors that match these patterns are Broadwell-based or fit into this scheme. The model numbers may have suffixes that are not shown here.
Skylake (Core i3 6th generation) – 14 nm process technology
2 physical cores/4 threads
3–4 MB L3 cache
Introduced Q3'15
Socket 1151 LGA
2-channel DDR3L-1333/1600, DDR4-1866/2133
Integrated GPU Intel HD Graphics 530 (only i3-6098P have HD Graphics 510)
Variants
i3-6098P – 3.60 GHz
i3-6100T – 3.20 GHz
i3-6100 – 3.70 GHz
i3-6300T – 3.30 GHz
i3-6300 – 3.80 GHz
i3-6320 – 3.90 GHz
Core i5 (6th generation)
Skylake (Core i5 6th generation) – 14nm process technology
4 physical cores/4 threads
6 MB L3 cache
Introduced Q3'15
Socket 1151 LGA
2-channel DDR3L-1333/1600, DDR4-1866/2133
Integrated GPU Intel HD Graphics 530
Variants
i5-6300HQ – 2.30/3.20 GHz Turbo Boost
i5-6400T – 2.20 GHz/2.80 GHz Turbo Boost
i5-6400 – 2.70 GHz/3.30 GHz Turbo Boost
i5-6440hq
i5-6500T – 2.50 GHz/3.10 GHz Turbo Boost
i5-6500 – 3.20 GHz/3.60 GHz Turbo Boost
i5-6600T – 2.70 GHz/3.50 GHz Turbo Boost
i5-6600 – 3.30 GHz/3.90 GHz Turbo Boost
i5-6600K – 3.50 GHz/3.90 GHz Turbo Boost
Core i7 (6th generation)
Skylake (Core i7 6th generation) – 14nm process technology
4 physical cores/8 threads
8 MB L3 cache
Introduced Q3'15
Socket 1151 LGA
2-channel DDR3L-1333/1600, DDR4-1866/2133
Integrated GPU Intel HD Graphics 530
Variants
i7-6700T – 2.80 GHz/3.60 GHz Turbo Boost
i7-6700 – 3.40 GHz/4.00 GHz Turbo Boost
i7-6700K – 4.00 GHz/4.20 GHz Turbo Boost
Other Skylake processors
Many Skylake-based processors are not yet listed in this section: mobile i3/i5/i7 processors (U, H, and M suffixes), embedded i3/i5/i7 processors (E suffix), certain i7-67nn/i7-68nn/i7-69nn.
Skylake-based "Core X-series" processors (certain i7-78nn and i9-79nn models) can be found under current models.
64-bit processors: Intel 64 (7th generation) – Kaby Lake microarchitecture
64-bit processors: Intel 64 (8th and 9th generation) – Coffee Lake microarchitecture
64-bit processors: Intel 64 – Cannon Lake microarchitecture
64-bit processors: Intel 64 (10th generation) – Ice Lake microarchitecture
64-bit processors: Intel 64 (10th generation) – Comet Lake microarchitecture
64-bit processors: Intel 64 (11th generation) – Tiger Lake microarchitecture
64-bit processors: Intel 64 (12th generation) – Alder Lake microarchitecture
64-bit processors: Intel 64 (13th generation) – Raptor Lake microarchitecture
Intel Tera-Scale
2007: Teraflops Research Chip, an 80 core processor prototype.
2009: Single-chip Cloud Computer, a research microprocessor containing the most Intel Architecture cores ever integrated on a silicon CPU chip: 48.
Intel 805xx product codes
Intel discontinued the use of part numbers such as 80486 in the marketing of mainstream x86-architecture processors with the introduction of the Pentium brand in 1993. However, numerical codes, in the 805xx range, continued to be assigned to these processors for internal and part numbering uses. The following is a list of such product codes in numerical order: